数字上变频问题

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  • So from what I understand, in the transmit side the digital up converters are implemented in the AD9862 chip but the interpolation is done in the FPGA. I believe in the receive side the down conversion is done in the FPGA. So why can't we do the same for the transmit side and implement the Digital UP Converters in the FPGA?

On the transmit side we use our own CIC to interpolate from whatever ratio comes over the USB to 32 MS/s. This is sent to the 9862 which then interpolates again by a factor of four to bring us to 128 MS/s. The up converter is in the 9862 as you say. In the receive side, the down conversion is done in the FPGA, because the 9862 does not have a down converter in the RX path. The bus going to the TX path on the 9862 is multiplexed (I then Q samples), and we run it at our normal clock rate of 64 MHz. This means we can only get 32 MS/s complex across it. If we did the up conversion in the FPGA, we would thus be limited to about a 12 MHz carrier.

  • The AD9862 chip contains interpolation filters as well. Could those be used instead of the CIC interpolators on the FPGA? In that way, both the up conversion and the interpolation would be done in the AD9862 chip and more space would be available on the FPGA?

We use those interpolation filters already, but they only do a factor of 4, so we still need a CIC in the FPGA.

  • What happened to the cic_int_shifter.v file in the USRP source? I am looking at re-enabling up conversion in the FPGA but cannot seem to locate this file.

It's still in: usrp/fpga/sdr_lib/cic_int_shifter.v

  • Is the data being clocked out of the USRP to DAC is at 64Msps?

More precisely, there are two interleaved channels, each running at 32MS/s. The AD9862 interpolates each stream by 4, giving two streams at 128MS/s.

  • There are two points that interpolation can happen - inside the AD9862 and internal to the FPGA. Within the FPGA, the CIC filter is the interpolating structure and has a variable rate, whereas the AD9862 has a fixed interpolation rate of 2x if a real-only signal is being used, or 4x is possible if interleaved with I/Q at 64Msps - giving the sample rate of I/Q 32Msps.Is that correct?

Yes.

  • I am unsure what the minimum interpolating rate of the CIC is, or the maximum for that matter?

It's probably 1 or 2, though I doubt it's been tested. The (workable) maximum is determined by the width of the intermediate stages of the CIC. I believe we're good to 128 in the FPGA CIC.

  • Who sets the interpolation rate of the CIC internal to the FPGA to get from the specified number of samples per symbol from a modulator block in GNU Radio to a number that the CIC can interpolate into 64Msps?

The code in usrp_standard.cc controls the FPGA interpolation rate. The rates do not have to be powers of two. From the user point of view the net interpolation rate must be in [4, 512] and a multiple of 4. This is all controlled in usrp_standard.cc.

  • There are 2 complex interpolators implemented in the FPGA (say int0, and int1). There are 4 real (ie, 2 complex) up converters implemented in the DAC chips (say DAC0, DAC1, DAC2, DAC3). The mux routes I and Q of int0 and int1 to the appropriate DACs. Is it true that DAC0,1 are hardwired to the TXA side of the USRP and dac2,3 to the TXB? Also, is the second complex interpolator used only if nchannels = 2?

Yes.

  • I found out that the max TX freq is limited in usrp_standard.cc to 44MHz (since USE_FPGA_TX_CORDIC is undefined). Now, since a 128MSps should safely ensure 64MHz, what is actually imposing that limitation?

Its set by the passband of the interpolator in the AD9862. The digital up converters in the AD9862 don't allow you to set the frequency to values close to the Nyquist frequencies (from 44MHz to 84MHz). Since it samples at 128 MHz, the prohibited ranges are around multiples of 64 MHz.

  • I'm having trouble understanding exactly how to go about sending two independent, real-valued signals to different SMA connectors on the same transmit daughterboards?

As the software is currently built, you cannot send two independent, real-valued signals to different connectors on the same transmit daughterboard. The reason is that we are using the digital up-converters in the AD9862, and have the AD9862's configured in "Dual Channel Complex DAC Data" mode. See pages 20-21 of the AD9862 datasheet. If you only need two independent TX channels, the quick fix is to use two Basic Tx daughterboards. This is supported. Just tell the USRP that you're using two channels of data, and then provide a stream with two interleaved channels of I & Q data. An additional thought is that if you don't need digital up-conversion, I don't think it would take much to get two independent channels out. You should be able to use the existing FPGA and host code, and just manually jam the right magic values into the AD9862 registers 19 and 20. Make sure that you continue to run the 4x interpolator on the AD9862 so all the data rates remain the same. You can write the AD9862 regs from python using:

u = usrp.sink_s(...)
u._write_9862(which_codec, regno, value) # note the leading _ character
# which_codec is 0 or 1 for side A or B

Look in usrp_standard.cc to see how we normally setup these registers.

  • At what rate should I send the samples to the tx_chains? Is every 4 clock cycles? They seem to be controlled by tx_strobe, but I failed to understand what this signal actually mean.

The minimum interpolation rate is 4 due to the CIC filter limitations, so once every 4 will yield one side of the spectrum. I believe 128 is the other end of the spectrum, but you should set a constant for the rate so we can test with different ones. The tx_strobe happens once every rate clock cycles - with which it will send in a new sample. That strobe sends a new value down the TX stream and reads a new one ready for the next tx_strobe.

  • What is the point of the bus_reset and the clear_status signal? They are both input to current tx_buffer.

I am not sure of this - but I am assuming to stop/reset the transmit path and clear any status messages respectively.

  • We have multiple USRPs clock-synchronized, but we haven't found a way to set things up so that the different sample streams hit the D/A converters at the same clock.

We have gotten multiple USRPs synchronized for receive. That FPGA code and host code is in the subversion. For transmit, the problem could be a bit more difficult, depending on whether you can deal with a constant phase difference between the transmitting USRPs or not (MIMO vs beam forming). If you need the phases to be identical between the USRPs then you will have to change the verilog such that you are no longer using the digital up converters in the AD9862 and instead implement the DUC in the FPGA. This is because there's no way to directly control the phase accumulator in the AD9862. If you can deal with a constant phase offset, then a strategy similar to what Marin used for Rx should work for TX.

  • My questions are regarding tx_chain.v. I am a bit confused as to how the flow of the code would proceed. There is no "always" statement in the code.

This is just wiring a couple things together to get the transmission chain to work at the full clock rate. There are 3 main components here: a phase accumulator, a CORDIC and an interpolating CIC filter. The baseband signals are fed into the CORDIC along with a phase from the phase accumulator. For each sample that goes in, the phase accumulator rotates. This generates an IF that is mixed with your baseband signal. The interpolating CIC filter gets your baseband signal up to the proper sample rate to feed the DACs.



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注：Digital Upconverter Questions（原文出处，翻译整理仅供参考!）